A. Technical Field
The present invention relates to interleaved analog-to-digital converters, and more particularly, to systems, devices, and methods of calibrating channel-to-channel mismatch error caused by one or more sources in interleaved analog-to-digital converters.
B. Background of the Invention
Time interleaved analog-to-digital converter (I-ADC) technology allows for power-efficient, high-speed sampling and digitization of analog input signals. In single ADC channel architectures, three competing parameters 1) precision, 2) speed, and 3) power are typically traded against each other. An I-ADC architecture allows the challenges of achieving high levels of precision to be separated from the challenges of operating at high speeds. In this way, power consumption required to achieve a given sampling rate may be optimized. Generally, I-ADC technology is the preferred option to achieve extremely high-speed sampling rates.
An I-ADC is a type of converter array with multiple parallel sampling channels. The sampling frequency of each channel does not need to satisfy the Nyquist criterion individually, rather the sampling frequency of the combined output of all channels in the I-ADC should satisfy the Nyquist criterion. Under ideal conditions, the sampling rate of I-ADCs increases proportionally to the number of interleaved parallel ADC channels. In practice, each ADC channel introduces a number of component errors, such as phase shift errors in the clock signals. I-ADCs are known to give rise to new performance limiting errors that are caused by transfer path mismatch (e.g. propagation delay), gain, and offset mismatch between the multiple ADC channels.
The types of mismatch that requires calibration can generally be categorized into timing skew mismatch, bandwidth mismatch, offset mismatch, gain mismatch, and static non-linearity mismatch. The combined channel mismatch error may modulate nonlinearly with the unknown analog input signal and create signal-dependent error terms that further limit I-ADC performance. Moreover, drifts temperature, power supply voltage, and other environmental conditions may change the mismatch error over time, which requires additional mismatch calibration.
Although many solutions have been proposed to minimize, compensate, or calibrate the various sources of mismatch, mismatch error remains a bottleneck for high-precision, high-speed sampling of high-frequency input signals.
In order to correct for each mismatch error, a method is required for correlating the error of interest with an observable output signal, which is often the digital output signal of one or more channels forming the array in the I-ADC. To achieve convergence, the correlation of each mismatch error to its observable output signal must be sufficiently large for the analog input signal present at the ADC input. Additionally, the mismatch error must be sufficiently independent of other mismatch errors.
What is needed are systems, devices, and methods for background calibration of I-ADC circuits to overcome the above-described limitations.